Who:

Accellera, the Electronic Design Automation (EDA) organization focused on language-based design standards, invites the electronic design community to attend its panel session at GSPx, an event supported by the organization, in Santa Clara, California.

What:

Members of Accellera's working group will present how Accellera standards such as the Property Specification Language (PSL), also known as IEEE Std™ 1850, and the SystemVerilog Hardware Design and Verification Language (HDVL), also known as IEEE P1800, can be used to improve IP delivery and verification.

Abstract: The problem of ensuring the quality and usability of IP for system designs is becoming a major concern for system integrators and IC manufacturers. This is particularly true for complex, highly configurable components such as DSPs. To solve this problem, the industry is turning to standards organizations such as Accellera to enhance standard design and verification languages to keep pace with the industry's need for advanced verification technology.

The use of assertions and formal techniques is a recognized path to dealing with these issues. The combination of assertion-based techniques with standard design languages is an effective way to bring this technology to the broad base of users who need it. This panel discusses how these techniques are being adopted by IP designers to solve their verification and integration problems. It also discusses what additional work is needed to ensure interoperability between IP blocks that may have been designed by different groups or companies and may be using different languages and methodologies for design and verification.

Moderator: Victor Berman - Cadence Design

Panelists: Cesar Quiroz, CoWare; Cary Ussery, Improv Design; Kenneth Larsen, Mentor; Bassam Tabbara, Novas; Rich Faris, Real Intent; Tom Anderson, Synopsys

When/Where:

Wednesday, October 26, 9-10am; Room 204, Santa Clara Convention Center, Santa Clara, California

For More Information:

For more information about Accellera and Accellera standards, please visit www.accellera.org.

For more information about GSPx, please visit www.gspx.com.

About PSL

The PSL standard addresses the shortcomings of natural language forms of design specification. It allows engineers to capture the functional specifications of logic design in a way that is unambiguous, effective and concise using the notion of properties and assertions. The expressiveness of PSL allows users to easily document and specify design behavior with properties. Furthermore, the formal nature of PSL enables the use of automatic tools to verify design properties written in this language, saving time and effort in the design verification cycle.

About SystemVerilog

SystemVerilog is a unified hardware design, specification and verification language standard that is based on the work done by Accellera. It adds powerful design and verification capabilities to the Verilog hardware description language (HDL) with constructs for architectural, algorithmic and transaction-based modeling. It also offers an environment for automated testbench generation, and provides assertions to describe design functionality, including complex protocols, to drive verification using simulation or formal verification techniques. Its C-API (Application Programming Interface) provides the ability to mix Verilog HDL and C/C++ constructs.

About Accellera

Accellera provides design standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA standards that lower the cost of designing commercial IC and EDA products. As a result of Accellera's partnership with the IEEE, Accellera standards are provided to the IEEE standards body for formalization and ongoing change control. For more information about Accellera, please visit www.accellera.org.

Accellera acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

Press Contact:
Georgia Marszalek
ValleyPR for Accellera
650 345-7477
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